Midterm Cheatsheet

Data type sizes and alignments on x86

Type	Size	Alignment
`char`, `int8_t`	1 byte	1 byte
`short`, `int16_t`	2 bytes	2 bytes
`int`, `long`, `int32_t`	4 bytes	4 bytes
`T *`	4 bytes	4 bytes
`long long`, `int64_t`	8 bytes	4 bytes in structs**
`float`	4 bytes	4 bytes
`double`	8 bytes	4 bytes in structs**

**Alignment on x86 is in part compiler dependent, and GCC enforces different alignment constraints for values in structs vs. values on the stack. (Some people consider this a bug.) For long long and double values on the stack, GCC 4.7.0 (the CS50 Appliance version) enforces 8 byte alignment; and GCC reports __alignof__(double) == 8 for the double type.

x86 registers

%eax

Accumulator. Lower 16 bits (0-15) called %ax. Bits 0-7 called %al, bits 8-15 called %ah.

%ebx`, `%ecx`, `%edx

General-purpose registers with %*x, %*l, %*h variants.

%esi`, `%edi

Other general-purpose registers. Lower 16 bits (0-15) called %si, %di.

%esp

Stack pointer.

%ebp

Frame pointer or general-purpose register.

%eip

Instruction pointer.

x86 addressing modes for values

$V Immediate: constant value V

V can be an integer constant or the name of a global variable

%R Register

V Absolute memory: memory contents starting at address V

(%`<em>`R`</em>`)

Indirect memory: memory contents starting at %R

V(%R) Indirect memory, base + displacement: memory contents starting at address V + %R

V(%R1,%R2,s) Indirect memory, general indexed: memory contents starting at V + %R1 + (%R2×s)

Many parts can be left off. V, %R1, and %R2 default to 0. s defaults to 1; it can only be 1, 2, 4, or 8.

x86 addressing modes for instruction addresses (`jmp`, `call`)

V Absolute: jump to the address V

*E Relative: jump to the address contained in expression E (see above for expressions)

Some x86 instructions

movl SRC, DST

Move 4 bytes from SRC to DEST

leal SRC, DST
SRC` must refer to a memory address (possibly indirectly) and `DST

must be a register. Sets DST to the address SRC refers to.

Example: leal (%eax), %ebx is equivalent to movl %eax, %ebx.

pushl SRC

Decrement %esp by 4, then move 4 bytes from SRC to (%esp)

Like subl $4, %esp; movl SRC, (%esp)

popl DST

Move 4 bytes from (%esp) into DST, then increment %esp by 4

Like movl (%esp), DST; addl $4, %esp

jmp L

Unconditional branch to L

Like “movl L, %eip”

call F

Push the return address (the address of the next instruction) and jump to F

Like “subl $4, %esp; movl [NEXT %eip], (%esp); jmp F”

ret

Return from a call: pop the return address and jump to it.

Like “popl %eip”

leave

Equivalent to movl %ebp, %esp; popl %ebp

addl SRC, DST (subl, imull, mull) Arithmetic operations: DST = DST op SRC.

cmpl SRC, DST

Like subl SRC, DST, but only set condition codes (DST is not modified)

andl SRC, DST (orl, xorl) Bitwise operations

testl SRC, DST

Like andl SRC, DST, but only set condition codes (DST is not modified)

sall SRC, DST

Shift DST left by SRC bits (SRC defaults to 1), filling in with 0 bits

shrl SRC, DST (sarl SRC, DST) Shift DST right by SRC bits, filling in with 0 bits for shrl (copies of DST sign bit for sarl)

je L [or jz], jne L [or jnz] Conditional branch if equal (zero), not equal (not zero); uses condition flags

jg`, `jge`, `jl`, `jle

Conditional branches for signed comparison

ja`, `jae`, `jb`, `jbe